The semiconductor integrated circuit (IC) industry has experienced rapid growth. Over the course of this growth, functional density of the devices has generally increased by the device feature size or geometry has decreased. This scaling down process generally provides benefits by increasing production efficiency, lower costs, and/or improving performance. Such scaling down has also increased complexities of processing and manufacturing ICs.
Likewise, the increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices. These multi-gate devices include multi-gate fin-type field-effect transistors (finFET), also referred to as finFET devices, so called because the channel is formed on a “fin” that extends from the substrate. FinFET devices allow for shrinking the gate width of devices while providing a gate on the sides and/or top of the fin including the channel region, in some instances.
FinFET device structures are different from device structures of planar metal-oxide-semiconductor field-effect transistors (MOSFETs). The manufacturing and the modeling of device performance of finFET devices face unique challenges.